DAQ PCI-FRM01 Bedienungsanleitung PDF herunterladen (Seite 10)

Application Note (AN241)

PCI-FRM01 Register Level Application Guide

Interrupt

Reserved

‘0’

LVDS

Reserved

‘0’

Reserved

‘0’

Reserved

‘0’

Global

When any of the above interrupt sources need

the processing, it will be changed '1'.

‘0’

31-16

Reserved

For future use

All ‘0’

For more information, refer AD5324 manual.

(2) INT_SEL

Select the Level Trigger and Edge Trigger of Interrup Input.

01234567891011121314

Status Clear C0

Reserved

INTERRUPT Clear Register Bit Position & meaning

C14

16 15

If it is “0”, it is a Level Trigger. If it is “1”, it is a Rising Edge Trigger.

(3) INT_EN

Each interrupt source is to enable the interrupt.

15 01234567891011121314

G Enable E0

Reserved

INTERRUPT Enable Register Bit Position & meaning

E14

If each bit is ‘1’, the device interrupt for corresponding bit will be enabled.

The bit 15 is Global Interrupt Enable. This bit is set to '1' to enable all interrupts.

(4) INT_SRC

INT_STA appear on the register, the interrupt request output of the device is latched at the rising

edge of the signal. Thus, it is not Level Trigger, it is an indication of Edge Triggere.

So, it can be cleared and requested the interrupt. On the other hand, in the INT_SRN, it represents

current output signal state of the current device.

01234567891011121314

Interrupt Source S0

Reserved

INTERRUPT Source Indicator Bit Position & meaning

S14

1 2 ... 5 6 7 8 9 10 11 12 13 14

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